65nm BCD Power Management Platform

65nm BCD process is leading the low voltage market segment with the highest power efficiency, best digital integration capability and superior cost effectiveness through both the smallest die size and low mask count.

The platform provides significant material competitive advantages for any type of power management chip up to 24V operation regardless of application, including a wide variety of products such as: PMICs, load switches, DC-DC converters, LED drivers, motor drivers, battery management, analog and digital controllers, and more. 

The process includes leading edge power LDMOS transistors with the best available Rdson and Qgd parameters. In addition, multiple chips can be integrated to a single monolithic IC solution replacing a multiple chip module for an improved system cost structure and system performance. Process developments aim to maintain minimum layer count with aggressive power performance.

Tower Semiconductor’s power transistors are fully isolated to withstand high currents, all with an ultra-low Rdson, e.g. less than 0.8mΩ*mm² for the 5V operation LDMOS. For products which operate at the megahertz (MHz) switching frequencies, the 65nm BCD power transistors benefit from a very low Qgd. In addition, very low metal resistance is achieved using a single or dual 3.3um top thick copper. The 65nm BCD also offers aggressive 113Kgate per mm² 5V digital density and an 850Kgate per mm² 1.2V digital library.