Industry & Company Events

"Future Trends in Imaging Beyond the Mobile Market"

Dr. Amol Kalburge

Presenting: Ronen Hasnes, PDK Section Head | TowerJazz

Qin Lei

Erez Sarig - Director of BD & Marketing PM/MS BU

TowerJazz Dr. Paul Hurwitz will be taking part of the panel

By Dr. Paul Hurwitz

Masanobu Kumazaki

By: Ronen Hasnes

Samir Chaudhry - Director, Design Enablement, TowerJazz
James Pond (CTO, Lumerical)
Gilles Lamant (Distinguished Engineer, Cadence)
Pei-Der Tseng (Design Engineering Architect, Cadence Design Systems)
Rich Goldman (Head of Marketing, Lumerical)

Presentor: Dr. Amol Kalburge

AJ ElJallad - Senior Sales Director, Tower Semiconductor

6:00pm - 6:30pm Detroit
Online - https://2020.auto-sens.com/agenda/session/334233

Presenter: Mike Scott - Director, Tower Semiconductor USA Aerospace & Defense

Samir Chaudhry - Director, Design Enablement
Ofer Tamir - Senior Director Design Enablement
John Stabenow - Siemens Industries Software

https://events.sw.siemens.com/en-US/realizelive/agenda?agendaPath=session/542767

Abstract: Established and emerging wireless and wireline applications such as 5G, WiFi and 400-800G optical networking are driving the demand for highly optimized RFIC solutions. Typical RF/mmWave design flows rely on the use of multiple EDA tools often sourced from multiple EDA vendors. This is inherently inefficient and often error prone leading to delays in getting a product to market. In addition, there exist multiple combinations of design tools and flows that prevent a foundry from providing a golden reference flow that can be used by a large portions of the design community. In this paper we present a silicon validated unified RFIC design flow using the Virtuoso RF. The design flow is based on a high-power SP4T switch design in Tower Semiconductor’s CS18QT9x1 foundry technology. RF SOI switch designs offer a useful test-case for the Virtuoso RF design flow as they require co-design and co-optimization of both the silicon and the package which is a key strength of this design flow. The design flow will be used to present a consistent modeling and simulation methodology. A seamless hand-off between PDK provided model, metal interconnect extraction within the p-cell, metal interconnect modeling outside the p-cell using EMX and Clarity, and the flip-chip package will be presented, while maintaining a single unified database that is used for tape-out. Silicon validation of key small and large-signal metrics will be presented highlighting the importance of the tight interaction between foundry Virtuoso PDK and package modeling using EMX and Clarity.

https://events.cadence.com/event/70560da2-887d-4795-a8bc-1dcad2d95ca6/websitePage:a4c8ddce-9c7a-43e1-a4f8-2333a8e328a2

Abstract: The demand for silicon photonics technology is growing with popular applications such as datacom (5G), artificial intelligence (AI), sensing, quantum computing and autonomous driving due to the improved bandwidth, sensing capabilities and reduced power consumption of photonic devices. For a typical photonic integrated circuits (PICs) design, designers use a combination of silicon validated components from a process design kit (PDK) and custom components that adhere to the foundry process design rules. However, as component layout designs and simulations are typically performed using different design tools and platforms, it is challenging to maintain the components’ compliance with the foundry process, while creating accurate compact models for efficient simulations. With a goal to reduce the design cycle time of custom photonic components for PICs designs, this work demonstrates a design workflow that facilitates photonic component layout, device simulation, compact model generation, and circuit simulation. This workflow leverages design tools from Cadence and Ansys-Lumerical, and a foundry silicon photonics PDK (PH18) from Tower Semiconductor. In this workflow, physical layout is the initial step of a custom photonic component design, where the curvilinear/polygon-based component shapes are drawn in Cadence Virtuoso Layout Suite by using the PH18 PDK. To assist device simulations on a custom design, the PDK provides a process file that contains all the information necessary for Lumerical DEVICE Suite to directly generate a 3D model from the design layout and to simulate it accurately for the foundry process. The device simulation results can then be used by the Lumerical CML Compiler to automatically build high-quality optical compact models in both the Lumerical INTERCONNECT and Verilog-A formats for different stages of the PIC design flow.

https://events.cadence.com/event/70560da2-887d-4795-a8bc-1dcad2d95ca6/websitePage:a4c8ddce-9c7a-43e1-a4f8-2333a8e328a2

Speaker: Lei Qin, Vice President of China Operations, Tower Semiconductor Ltd.

by Erez Sarig, Director of Business Development & Marketing

Tower and Synopsys collaboration on SiPho design environment for Tower PH18 180nm SiPho platform
by Ofer Tamir, Managing Director Design Enablement & Support

Speaker: Rachel Xie, Sr. Director, Deputy Country Manager of China

Venue: 上海世博展览馆一层1号厅 高峰论坛会场
1F-Hall 1, Shanghai World EXPO Exhibition & Convention Center Summit Forum

Speaker: Cai Yuna, FAE Manager

Venue: 上海世博展览馆B2层2号会议室 专题论坛(VIII)
B2 – Meeting Room 2, Shanghai World EXPO Exhibition & Convention Center Subject Forum(VIII)