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ChipEx 2018 - Event Summary
May 01, 2018
Tel Aviv Fairgrounds, Israel
IS Americas - Event Summary
October 11 - 12, 2018
Hyatt Centric Fisherman's Wharf
San Francisco, CA, USA
Presentation Schedule
Don’t miss TowerJazz presentation:
13:00-13:30 | October 12
Hyatt Centric Fisherman's Wharf
Dr. Amos Fenigstein
"Future Trends in Imaging Beyond the Mobile Market"
Advanced Photonics IC Design Webinar - Event Summary
October 18, 2018
US/Pacific: 9:00AM
Asia/China: 4:00PM
EU/London: 9:00AM
Vehicle Connectivity Summit 2018 - Event Summary
October 18 - 19, 2018
Shanghai, China
Presentation Schedule
Don’t miss TowerJazz presentations:
Date: October 18
Hour: 15:30 - 16:10
"Specialty Analog Foundry Solutions for Connected and Automated Vehicles"
Dr. Amol Kalburge
User2User Europe - Event Summary
November 26, 2018
Park Hilton,
Munich, Germany
Don’t miss TowerJazz presentations:
Track: IC Design (Physical Implementation and Verification)
Room: Salon Rumford
Time: 14:30
Adding DFM statistics for DRC rules to allow customer estimate error severances when negotiate DRC waive from the Fab
Presenting: Ronen Hasnes, PDK Section Head | TowerJazz
SURGE Herzliya - Event Summary
November 28, 2018
Dan Accadia Herzliya Hotel,
Herzliya, Israel
ICCAD 2018 - Event Summary
November 29 - 30, 2018
Zhuhai International Convention & Exhibition Center
Zhuhai, China
Booth: #112\113
Don’t miss TowerJazz presentation:
November 30
"Analog Products in 65nm"
Qin Lei
APEC - Event Summary
March 17 - 21, 2019
Anaheim Convention Center
Anaheim, CA
Booth: #328
Presentation Schedule
Don’t miss TowerJazz presentations:
March 19, 2019 / Room 213B
08:30AM - 11:55 AM
Market Research: 65nm for Power Management IC - Sub 90nm PM Market Trends and Technology Advantages
Erez Sarig - Director of BD & Marketing PM/MS BU
GOMAC - Event Summary
March 25 - 28, 2019
DoubleTree by Hilton Hotel Albuquerque
201 Marquette Avenue Northwest
Albuquerque, New Mexico
Mentor and TowerJazz Automotive Workshop - Event Summary
July 04, 2019
Newbury Berkshire UK
9:00 -15:30 EU/London
TowerJazz & Synopsys Webinar: Foundry Silicon Photonics Process - Event Summary
July 16, 2019
Join us at one of those hours:
10 am CET (For EU and Asia audiences)
10 am PDT (For U.S. audience)

One hour is planned for this webinar, including Q&A sessions.
HEART - Event Summary
August 18 - 21, 2019
San Diego, CA
EPE’ 19 – ECCE EUROPE - Event Summary
September 03 - 05, 2019
Magazzini del cotone Conference Centre
Via Magazzini del Cotone
16128 Genova, Italy
Booth: #24
Presentation Schedule
Don’t miss TowerJazz presentations:
Wednesday, September 4th
Time: 17:15
Location: Austro Room
Integrated Power Management Future Trends and Solutions
SOI Consortium China - Event Summary
September 16 - 17, 2019
Pudong Shangri-La Hotel
Shanghai, China
Presentation Schedule
Don’t miss TowerJazz presentations:

Session 1 - Deployment
Panel Discussion: 5G Deployment in China
TowerJazz Dr. Paul Hurwitz will be taking part of the panel

Session 3 - RF Value Chain
Specialized RFSOI foundry technology solutions to support rapid new product development
By Dr. Paul Hurwitz
Japan SOI Symposium 2019 - Event Summary
October 30 - 31, 2019
Yokohama @ Landmark Tower, 25F
Yubinbango220-8125, Yokohama, Kanagawa Prefecture Minato Mirai, Nishi 2-chome No. 2 No. 1 2
TowerJazz Presentation
Don’t miss TowerJazz presentations:
Oct. 31, 2019 | 11:55 – 12:20

Worlds first open commercial silicon photonics process and PDK from TowerJazz,
Masanobu Kumazaki
User2User Europe - Event Summary
November 04, 2019
Hilton Munich Airport
Terminalstreet Mitte 20
TowerJazz Presentation
Don’t miss TowerJazz presentations:
November 4th, 2019
Track: IC Design (Physical Implementation and Verification)
Time: 14:00-14:30
Implementation of a Transistor-Level DSPF Extraction Flow for Power Integrity Analysis
By: Ronen Hasnes
Mentor and TowerJazz Automotive Workshop - Event Summary
November 06, 2019
Mentor Graphics (Deutschland) GmbH
Arnulfstraße 201
80634 München
Mentor and TowerJazz Automotive Workshop - Event Summary
November 21, 2019
Mentor, A Siemens Business
46871 Bayside Parkway
Fremont, CA
USA 94538
DesignCon 2020 - Event Summary
January 28 - 30, 2020
Santa Clara Convention Center
Santa Clara, CA
Presentation Schedule
Don’t miss TowerJazz presentations:
January 28, 2020 / Ballroom A
1:30pm - 4:30pm
Tutorial – Electronic/Photonic IC Design for 5G RF Applications
Samir Chaudhry - Director, Design Enablement, TowerJazz
James Pond (CTO, Lumerical)
Gilles Lamant (Distinguished Engineer, Cadence)
Pei-Der Tseng (Design Engineering Architect, Cadence Design Systems)
Rich Goldman (Head of Marketing, Lumerical)
Power Management Technical Webinar - Event Summary
April 21, 2020
16:00 pm Israel time / 15:00 pm CET
Free Online Webinar:
Leading Power Management Technology Addressing Market Trends and Requirements for Extended Power and High Voltage Applications
Autosense ONLINE 2020 - Event Summary
June 11, 2020
Online Presentation:
Automotive Radar - Technologies and Tradeoffs
Booth: #Online
Presentation Schedule
Don’t miss Tower Semiconductor ONLINE presentation
Thursday, June 11th - 4:30 PM BST
Liv e Q&A following the session
Automotive Radar: Technologies and Tradeoffs
Presentor: Dr. Amol Kalburge
The Sensors Show Virtual - Event Summary
July 22 - 23, 2020
Online event
Presentation Schedule
Don’t miss Tower Semiconductor ONLINE presentation:
July 23, 2020 - Online
TRACK B - Industry 4.0, Manufacturing & IoT
EDT - 18:10
CEST/PDT - 15:10
IoT Sensors for The Industrial and Harsh Environments
AJ ElJallad - Senior Sales Director, Tower Semiconductor
Autosens 2020 - Event Summary
November 17 - 19, 2020
Detroit, USA
Presentation Schedule
Don’t miss Semiconductor presentation:
Tuesday, November 17th, 2020
Emerging Role of Foundries in Bringing High Value Analog Products to Market
6:00pm - 6:30pm Detroit
Online -
NSREC 2020 - Event Summary
December 01 - 04, 2020
On-Line event - exhibit
December 1-3 – Manned Exhibits 11:30am-01:00pm EST
December 7-8 – Manned Exhibits 11:30am-01:00pm EST
Presentation Schedule
Don’t miss Tower Semiconductor presentations:
Friday, 12/4/2020
Time: 14:30 - 15:00
Tower's online booth
Tower Semiconductor Aerospace and Defense Technology Solutions
Presenter: Mike Scott - Director, Tower Semiconductor USA Aerospace & Defense
Tower Semiconductor Webinar on Automotive Excellence – From Design to Volume Production - Event Summary
March 24, 2021
Online webinar
Session I - 9:30 AM London
Session II - 11 AM USA PST
Presentation Schedule
Don’t miss Tower Semiconductor presentation:
On-Demand - GROW
Enabling Tower’s Leading-Edge BCD and RF Technologies with Siemens EDA Design Tools
Samir Chaudhry - Director, Design Enablement
Ofer Tamir - Senior Director Design Enablement
John Stabenow - Siemens Industries Software

CadenceLIVE Americas 2021 - Event Summary
June 08 - 09, 2021
Digital Event
Presentation Schedule
Don’t miss Tower Semiconductor presentation:
Wednesday, June 9th
10:50 - 11:20
5G / RF
Silicon-Validated RFIC Package Co-Design Using Virtuoso RF Solution in Tower Semiconductor's CS18 RF SOI Technology
Abstract: Established and emerging wireless and wireline applications such as 5G, WiFi and 400-800G optical networking are driving the demand for highly optimized RFIC solutions. Typical RF/mmWave design flows rely on the use of multiple EDA tools often sourced from multiple EDA vendors. This is inherently inefficient and often error prone leading to delays in getting a product to market. In addition, there exist multiple combinations of design tools and flows that prevent a foundry from providing a golden reference flow that can be used by a large portions of the design community. In this paper we present a silicon validated unified RFIC design flow using the Virtuoso RF. The design flow is based on a high-power SP4T switch design in Tower Semiconductor’s CS18QT9x1 foundry technology. RF SOI switch designs offer a useful test-case for the Virtuoso RF design flow as they require co-design and co-optimization of both the silicon and the package which is a key strength of this design flow. The design flow will be used to present a consistent modeling and simulation methodology. A seamless hand-off between PDK provided model, metal interconnect extraction within the p-cell, metal interconnect modeling outside the p-cell using EMX and Clarity, and the flip-chip package will be presented, while maintaining a single unified database that is used for tape-out. Silicon validation of key small and large-signal metrics will be presented highlighting the importance of the tight interaction between foundry Virtuoso PDK and package modeling using EMX and Clarity.
Tuesday, June 8th
12:00 - 12:30
Silicon Photonics
Streamlined Foundry-Compatible Custom Photonic IC Design with Ansys-Lumerical, Cadence Virtuoso Environment and Tower Semiconductor's Foundry PDK
Abstract: The demand for silicon photonics technology is growing with popular applications such as datacom (5G), artificial intelligence (AI), sensing, quantum computing and autonomous driving due to the improved bandwidth, sensing capabilities and reduced power consumption of photonic devices. For a typical photonic integrated circuits (PICs) design, designers use a combination of silicon validated components from a process design kit (PDK) and custom components that adhere to the foundry process design rules. However, as component layout designs and simulations are typically performed using different design tools and platforms, it is challenging to maintain the components’ compliance with the foundry process, while creating accurate compact models for efficient simulations. With a goal to reduce the design cycle time of custom photonic components for PICs designs, this work demonstrates a design workflow that facilitates photonic component layout, device simulation, compact model generation, and circuit simulation. This workflow leverages design tools from Cadence and Ansys-Lumerical, and a foundry silicon photonics PDK (PH18) from Tower Semiconductor. In this workflow, physical layout is the initial step of a custom photonic component design, where the curvilinear/polygon-based component shapes are drawn in Cadence Virtuoso Layout Suite by using the PH18 PDK. To assist device simulations on a custom design, the PDK provides a process file that contains all the information necessary for Lumerical DEVICE Suite to directly generate a 3D model from the design layout and to simulate it accurately for the foundry process. The device simulation results can then be used by the Lumerical CML Compiler to automatically build high-quality optical compact models in both the Lumerical INTERCONNECT and Verilog-A formats for different stages of the PIC design flow.
CICD China 2021 - Event Summary
November 01 - 03, 2021
Guangzhou, China
Presentation Schedule
Don’t miss Tower Semiconductor presentations:
Date: Nov. 3rd, 2021 Wednesday
Venue: Huangpu Ballroom B, 1F, NARADA Hotel, Guangzhou
Time: 10:30-10:55
Sensing the World - Advanced CMOS Image Sensor Technology for 3D Imaging and Beyond
Speaker: Lei Qin, Vice President of China Operations, Tower Semiconductor Ltd.
2021 Annual Technical Global Symposium (TGS) – USA Session - Event Summary
November 16, 2021
Online - USA Session (9am Pacific)
2021 Annual Technical Global Symposium (TGS) – Europe / APAC Session - Event Summary
November 17, 2021
Online - Europe/APAC Session
9am Paris | 5pm Japan | 10am Israel
SNUG Israel 2022 - Event Summary
September 20, 2022
Daniel Hotel - Herzliya,
Presentation Schedule
Don’t miss Tower's presentation:
September 20th
Room: Typhoon
Track: AMS & Physical Verification
Time: 15:30-16:00
Advances in Silicon Photonics Design Enablement with Synopsys Tools
Speaker: Ofer Tamir - Director Design Enablement
Tower Semiconductor
ICCAD China 2022 - Event Summary
December 26 - 27, 2022
Guangzhou PWTC Expo, China
Booth: #311, 320
Presentation Schedule
Don’t miss Tower's presentations:
Date: Dec 26, 2022 Time:15:55-16:15
Venue: Xiamen International Conference & Exhibition Center, 1st Floor, C4
Tower Semiconductor – Where Analog and Value Meet
Speaker: Lei Qin, VP of China Operations, Tower Semiconductor Ltd.
Date: Dec 27, 2022
Time: 08:40-09:00
Venue: Xiamen International Conference & Exhibition Center
Advanced 300mm 65nm BCD Power Management Platform – Best-in-class Technology Solutions Addressing the Extensive Power Market Needs
Speaker: Min Wang, Sales & FAE Manager, Tower Semiconductor Ltd.
Image Sensor Europe – ISE - Event Summary
March 15 - 16, 2023
Park Plaza Hotel Victoria
London, UK
Presentation Schedule
Don’t miss Tower Semiconductor presentation:
March 15, 2023 11:45 am
Part of Session 1: Business and manufacturing updates
The CMOS image sensor landscape keeps evolving to address new applications, in Industry 4.0, medical, automotive or consumer imaging. CMOS foundries must adapt to the various ideas and concepts Image Sensor suppliers in order to stay relevant. In this talk, we will discuss some of the solutions developed by Foundries to expand the use of imaging technology, with examples in the fields:
• Infrared Imaging
• Charge domain BSI Global shutter solutions
• Above IC technologies going beyond Imaging.

Benoit Dupont, Sensors and Display Marketing Director at Tower Semiconductor

For agenda and additional details - Click here >
SNUG SV 2023 - Event Summary
March 29 - 30, 2023
Santa Clara Convention Center
Santa Clara, California, USA
Booth: #108
Siemens U2U USA 2023 - Event Summary
April 13, 2023
Santa Clara, California
CDNLive Silicon Valley 2023 - Event Summary
April 19 - 20, 2023
Santa Clara Convention Center
PCIM 2023 - Event Summary
May 09 - 11, 2023
Nürnberg, Germany
Booth: #6-146
Siemens U2U Europe 2023 - Event Summary
May 11, 2023
Munich, Germany
Presentation Schedule
Don’t miss Tower Semiconductor presentations:
May 11, 2023 at 1:40pm - 2:10pm
Session Track: IC Backend Track 1
Location: Ballroom Munich I + II
Charging damage from plasma processing can be reduced through process architecture and plasma process optimization, but not all damage can be prevented. Antenna area ratio design rules are commonly used in the semiconductor industry to ensure that the remaining charging does not damage circuits. Capturing all possible contributions to device damage in a few simple antenna design rules is not possible. The presence of a Buried Oxide layer and Deep trenches in TS18PM SOI platform further complicates the creation of practical antenna design rules. Such rules were not found in the literature. This work describes the topologies specific for TS18PM SOI and how the different schemes of antenna rules were built and coded.

Ofer Tamir, Managing Director for Design Enablement and Support

For agenda and additional details - Click here >

TGS 2023 Europe - Event Summary
September 06, 2023
Hyatt Place Amsterdam Airport, Netherlands
ION 2023 - Event Summary
September 11 - 15, 2023
Hyatt Regency
Denver, Colorado, USA
Booth: #113
TGS 2023 China - Event Summary
September 12, 2023
Aloft Shanghai Zhangjiang Haike
ECOC 2023
October 02 - 04, 2023
Scottish Event Campus Ltd
Glasgow, Scotland

Booth: #833
CDNLive Europe 2023
October 10 - 11, 2023
Hilton Munich Park
TGS 2023 USA
November 15, 2023
Hyatt Regency Santa Clara, CA
Photonics West
January 30 - 01, 2024
The Moscone Center
747 Howard Street
San Francisco, California 94103
Booth: #2451
APEC 2024
February 25 - 29, 2024
Long Beach Convention & Entertainment Center
300 East Ocean Boulevard
Long Beach, CA 90802
Booth: #625
OFC 2024
March 24 - 28, 2024
San Diego Convention Center, California, USA
Booth: #4608
SPIE 2024
April 21 - 25, 2024
National Harbor, Maryland
Booth: #724
IMS 2024
June 18 - 20, 2024
Walter E. Washington Convention Center
Washington, DC
Booth: #830

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