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RFIC and mmWave Design Solutions for Cadence Tools on Tower’s SiGe BiCMOS and RF SOI Technologies
Overview
RF and mmWave design success rely on tight and productive collaboration between foundry design enablement teams and EDA vendors. Tower Semiconductors has a long-term, on-going partnership with Cadence Design Systems. Based on expertise and vast market experience, this well-established collaboration is designed to provide a holistic design environment for Tower’s industry leading SiGe BiCMOS and RF SOI technologies.
In this talk, we’ll present an overview of the collaboration between Tower and Cadence, discuss case study examples of RF designs leveraging the capabilities in Virtuoso RF and it’s integration with tools for EM simulation of passives, layout synthesis, safe operating area checks, and EMIR verification.
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PRESENTED BY
Dr. Samir Chaudhry
Director of Design Enablement, Tower Semiconductor
Dr. Chaudhry has been leading the Design Kit and Modeling activities for Tower Semiconductor since 2008. Prior to this, he led the SPICE modeling group at Jazz Semiconductor. His research interests include RF CMOS and statistical modeling. He has worked with the Compact Modeling Council in developing industry standard compact models for circuit simulation. Prior to joining Jazz, he was a Distinguished Member of Technical Staff with Bell Labs, where he worked on Technology CAD and device modeling for scaled silicon technologies. He has authored over 25 journal publications and has 30 patents in the field of silicon technology.
