RFIC and mmWave Design Solutions for Cadence Tools on Tower’s SiGe BiCMOS and RF SOI Technologies
December 1, 2020 |
RF and mmWave design success rely on tight and productive collaboration between foundry design enablement teams and EDA vendors. Tower Semiconductors has a long-term, on-going partnership with Cadence Design Systems. Based on expertise and vast market experience, this well-established collaboration is designed to provide a holistic design environment for Tower’s industry leading SiGe BiCMOS and RF SOI technologies.
In this talk, we’ll present an overview of the collaboration between Tower and Cadence, discuss case study examples of RF designs leveraging the capabilities in Virtuoso RF and it’s integration with tools for EM simulation of passives, layout synthesis, safe operating area checks, and EMIR verification.
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Dr. Samir Chaudhry
Director of Design Enablement, Tower Semiconductor
Mr. Yuval Shay
Group Director, Product Management in the Custom IC & PCB Group, Cadence
Mr. Shay joined Cadence in 2010 and currently leads the Virtuoso Design Platform product management team. Prior to joining Cadence, Yuval spent 15 years with STMicroelectronics in various design engineering roles, that focused on custom layout, digital place-and-route and mixed-signal design verification